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 HD74LS374
Octal D-type Edge-triggered Flip-Flops (with three-state outputs)
REJ03D0483-0200 Rev.2.00 Feb.18.2005 The HD74LS374, 8-bit register features totem-pole three-state outputs designed specifically for driving highlycapacitive or relatively low-impedance loads. The high-impedance third state and increased high-logic-level drive provide this register with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight flip-flops are edge-triggered D-type flipflops. On the positive transition the clock, the Q outputs will be set to the logic states that ware setup at the D inputs.
Features
* Ordering Information
Part Name HD74LS374P HD74LS374FPEL HD74LS374RPEL Package Type DILP-20 pin SOP-20 pin (JEITA) SOP-20 pin (JEDEC) Package Code (Previous Code) PRDP0020AC-B (DP-20NEV) PRSP0020DD-B (FP-20DAV) Package Abbreviation P FP Taping Abbreviation (Quantity) -- EL (2,000 pcs/reel) EL (1,000 pcs/reel)
PRSP0020DC-A RP (FP-20DBV) Note: Please consult the sales office for the above package availability.
Pin Arrangement
Output Control 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND
1 2 3 4 5 6 7 8 9 10
Q OE CK D CK D OE Q Q OE CK D CK D OE Q Q OE CK D CK D OE Q OE Q CK D CK D OE Q
20 19 18 17 16 15 14 13 12 11
VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q Clock
(Top view)
Rev.2.00, Feb.18.2005, page 1 of 7
HD74LS374
Function Table
Output control L L L H Inputs Clock L X D H L X X Outputs Q H L Q0 Z
Notes: H; high level, L; low level, X; irrelevant ; transition from low to high level Q0; level of Q before the indicated steady state input conditions were established Z; off (high-impedance) state of a three state output
Block Diagram
1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q
Q D CK D CK
Q D CK
Q D CK
Q D CK
Q D CK
Q D CK
Q D CK
Q
Output Control
1D
2D
3D
4D
5D
6D
7D
8D
Clock
Absolute Maximum Ratings
Item Supply voltage Input voltage Power dissipation Storage temperature Symbol VCC VIN PT Tstg Ratings 7 7 400 -65 to +150 Unit V V mW C
Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
Recommended Operating Conditions
Item Supply voltage Output voltage Output current Operating temperature Clock pulse width Data setup time Data hold time "H" Level "L" Level Symbol VCC VOH IOH IOL Topr tw tsu th Min 4.75 -- -- -- -20 15 15 20 0 Typ 5.00 -- -- -- 25 -- -- -- -- Max 5.25 5.5 -2.6 24 75 -- -- -- -- Unit V V mA mA C ns ns ns ns
Rev.2.00, Feb.18.2005, page 2 of 7
HD74LS374
Electrical Characteristics
(Ta = -20 to +75 C)
Item Input voltage Symbol VIH VIL VOH Output voltage VOL Output current IOZH IOZL IIH IIL II IOS ICC VIK min. 2.0 -- 2.4 -- -- -- -- -- -- -- -30 -- -- typ.* -- -- -- -- -- -- -- -- -- -- -- 27 -- max. -- 0.8 -- 0.4 0.5 20 -20 20 -0.4 0.1 -130 40 -1.5 Unit V V V V A A mA mA mA mA V Condition
VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V, IOH = -2.6 mA IOL = 12 mA VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V IOL = 24 mA VO = 2.7 V VCC = 5.25 V, VIH = 2 V, VIL = 0.8 V VO = 0.4 V VCC = 5.25 V, VI = 2.7 V VCC = 5.25 V, VI = 0.4 V VCC = 5.25 V, VI = 7 V VCC = 5.25 V VCC = 5.25 V, VI = 4.5 V (Output control) VCC = 4.75 V, IIN = -18 mA
Input current Short-circuit output current Supply current Input clamp voltage Note: * VCC = 5 V, Ta = 25C
Switching Characteristics
(VCC = 5 V, Ta = 25C)
Item Maximum clock frequency Propagation delay time Output enable time Output disable time Symbol max tPLH tPHL tZH tZL tHZ tLZ Inputs Clock Clock OC OC Output Q Q Q Q min. 35 -- -- -- -- -- -- typ. 50 15 19 20 21 12 14 max. -- 28 28 28 28 20 25 Unit MHz Condition
CL = 45 pF, RL = 667 ns CL = 5 pF, RL = 667
Rev.2.00, Feb.18.2005, page 3 of 7
HD74LS374
Testing Method
Test Circuit
VCC
Output
RL S1
Load circuit 1
4.5V 1Q
5k OC Input P.G. Zout = 50 1D 2D 2Q Output 3Q Output 4Q Output 5Q Output 6Q Output 7Q Output 8Q Output CL
S2
Same as Load Circuit 1. Same as Load Circuit 1. Same as Load Circuit 1. Same as Load Circuit 1. Same as Load Circuit 1. Same as Load Circuit 1. Same as Load Circuit 1.
See Function Table
3D 4D 5D 6D 7D 8D Clock
Input P.G. Zout = 50
Notes:
1. CL includes probe and jig capacitance. 2. All diodes are 1S2074(H).
Rev.2.00, Feb.18.2005, page 4 of 7
HD74LS374 Waveforms 1
tTLH 90% 1.3 V 10% tsu tTLH Clock 90% 90% 1.3 V 1.3 V 10% 10% tw tPLH Q S1, S2 Closed 1.3 V 1.3 V VOL tw tPHL VOH th tTHL 3V 1.3 V 0V 90% 1.3 V 10% tsu th tTHL 3V 1.3 V 0V
Data
Notes:
1. Input pulse; tTLH 15 ns, tTHL 6 ns Clock input; PRR = 1 MHz, duty cycle 50% Data input pulse; PRR = 500 kHz, duty cycle 50% 2. max: tTLH 2.5 ns, tTHL 2.5 ns
Waveforms 2
tTHL Output Control 90% 1.3V tTLH 90% 1.3V 3V 0V tLZ
10% tZL 4.5V
S1 closed, S2 open
10%
S1, S2 closed
Waveform A
1.3V tHZ 0.5V
1.5V VOL
tZH Waveform B
S1 open, S2 closed
VOH 1.3V 0V 1.5V 0.5V
S1, S2 closed
Notes:
1. Input pulse; tTLH 15 ns, tTHL 6 ns, PRR = 1 MHz, duty cycle 50% 2. Waveform A if for an output with internal conditions such that the output is low except when disabled by the output control. Waveform B is for an output with internal conditions such that the output is high except when disabled by the output control.
Rev.2.00, Feb.18.2005, page 5 of 7
HD74LS374
Package Dimensions
JEITA Package Code P-DIP20-6.3x24.5-2.54 RENESAS Code PRDP0020AC-B Previous Code DP-20NEV MASS[Typ.] 1.26g
D
20
11
1 0.89 b3
10
Z
E
Reference Symbol
Dimension in Millimeters Min Nom 7.62 24.50 6.30 25.40 7.00 5.08 0.51 0.40 0.48 1.30 0.19 0 2.29 2.54 0.25 0.31 15 2.79 1.27 2.54 0.56 Max
A
A1
e D E
L
1
A A1 b
p 3
e
bp
e1
c
b c
e Z
( Ni/Pd/Au plating )
L
JEITA Package Code P-SOP20-5.5x12.6-1.27
RENESAS Code PRSP0020DD-B
Previous Code FP-20DAV
MASS[Typ.] 0.31g
*1
D 11
F
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
20
bp
E
HE
Index mark
Reference Symbol
*2
c
Dimension in Millimeters Min Nom 12.60 5.50 Max 13.0
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
D E A2 A1 0.00
10 bp x M L1
0.10
0.20 2.20
A bp b1 c c
1
0.34
0.40
0.46
0.15
0.20
0.25
A
HE
0 7.50 7.80 1.27
8 8.00
y
e x y
A1
L
0.12 0.15 0.80 0.50
1
Detail F
Z L L 0.70 1.15
0.90
Rev.2.00, Feb.18.2005, page 6 of 7
HD74LS374
JEITA Package Code P-SOP20-7.5x12.8-1.27 RENESAS Code PRSP0020DC-A Previous Code FP-20DBV MASS[Typ.] 0.52g
*1
D
F 11 NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" @ DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT @ INCLUDE TRIM OFFSET.
20
bp
*2
HE
E
Index mark
Reference Symbol
c
Dimension in Millimeters Min Nom 12.80 7.50 Max 13.2
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
D E A2
10 bp x M L1
A1 A bp b1 c c
1
0.10
0.20
0.30 2.65
0.34
0.40
0.46
0.20
0.25
0.30
A
HE
0 10.00 10.40 1.27
8 10.65
A1
y L
e x y Z
0.12 0.15 0.935 0.40
1
Detail F
L L
0.70 1.45
1.27
Rev.2.00, Feb.18.2005, page 7 of 7
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
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Colophon .2.0


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